This invention relates to video display systems using a bit-mapped memory system for the video data, and more particularly to a semiconductor memory device for use in video displays or the like employing MOS random-access type read/write memory devices having both serial and parallel access.
Video displays are used with a wide variety of microcomputer-based systems, such as word processors, home computers, business computers and terminals, and the like. The data displayed on the video screen in a typical implementation of such system is read from a video memory which is bit-mapped, i.e., contains a one-for-one correspondance between the data bits stored in the memory array and the visable dots (called pixels) on the screen. The memory must be quite large, particularly for color video, and the access rate for video data must be quite high, 20 MHz or higher. Further, the microcomputer must be able to access the memory for update during a substantial fraction of the available time, making the operating speed of the memory more critical. The speed requirements might be met by bipolar or static MOS RAMs, but these are expensive and the bit density is low, adding to volume, complexity and cost of the system.
Memory devices of the N-channel silicon-gate MOS type employing one-transistor dynamic cells provide the smallest cell sizes, the highest bit density and lowest cost, and are thus the most widely used in computers and digital equipment. The extremely high volume of manufacture of such devices has resulted in a continuing reduction in cost according to "learning curve" theory, and this trend will continue as volume increases. In addition, improvements in line resolution and other process factors have made possible increases in bit density during the last ten years from 1K through 4K and 16K to 64K bits for devices now in volume production, with 256K-bit and 1-Megabit devices being designed. The MOS dynamic RAM has a relatively slow access time, however, compared to bipolar or static MOS RAMs, and in a given production run the faster dynamic RAMs are usually of lower yield and thus the most expensive.
Dynamic RAM devices with serial ports are disclosed in U.S. Pat. No. 4,347,587, issued to G. R. Mohan Rao, U.S. Pat. Nos. 4,281,401 and 4,330,852, issued to Donald J. Redwine Lionel S. White and G. R. Mohan Rao, and U.S. Pat. Nos. 4,322,635 and 4,321,695 issued to Donald J. Redwine, all assigned to Texas Instruments. These devices are similar in structure to the widely used 64K-bit "by 1" dynamic RAM devices as described in U.S. Pat. No. 4,239,993, but a 256-bit serial shift register is added for serial I/O.
It is the principal object of this invention to provide a dual-port semiconductor memory arangement for use in a system such as a video display by employing the same basic design of a widely-used MOS dynamic RAM, with additional sequential serial access capability to meet the high bit rate performance required by high resolution color video displays while also retaining the traditional parallel random access capability without performance loss, still retaining the economics of large scale manufacture and taking advantage of the design improvements of the MOS DRAM. Another object is to provide this improved serial/parallel type of access in memory devices which are of lower cost and susceptible to volume production, especially for applications such as video display systems.